Parity Error Detection in Embedded System
نویسندگان
چکیده
Abstract : In this article we describe one suitable approach that enables the designer to insert a boundary-scan and built-in-self-test concepts, as typical designfor-testability techniques in system-on-chip and multichip module embedded system design, for fault-effects detection. For transient error detection implementation of parity error detection into a 36-bit bus transceiver circuit (32-bit data & four parity bits) is given. The bus transceiver can be implemented as custom or semi-custom integrated circuit in submicron technology and low cost FPGA or CPLD circuit, core within a system-on-a-chip, or glue logic (bridge) within the multichip module.
منابع مشابه
An approach to fault detection and correction in design of systems using of Turbo codes
We present an approach to design of fault tolerant computing systems. In this paper, a technique is employed that enable the combination of several codes, in order to obtain flexibility in the design of error correcting codes. Code combining techniques are very effective, which one of these codes are turbo codes. The Algorithm-based fault tolerance techniques that to detect errors rely on the c...
متن کاملA compact AES core with on-line error-detection for FPGA applications with modest hardware resources
This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logic resources. The on-line error-detection is based on parity codes. The parity prediction is implemented in the AES encryption, decryption, and key expa...
متن کاملرویکردی برای حفاظت از عملیات های پردازش داده در سیستم های محاسباتی با استفاده از کدهای کانولوشن
Abstract We present a framework for algorithm-based fault tolerance methods in the design of fault tolerant computing systems. The ABFT error detection technique relies on the comparison of parity values computed in two ways. The parallel processing of input parity values produce output parity values comparable with parity values regenerated from the original processed outputs. Number data proc...
متن کاملDesign of nonlinear parity approach to fault detection and identification based on Takagi-Sugeno fuzzy model and unknown input observer in nonlinear systems
In this study, a novel fault detection scheme is developed for a class of nonlinear system in the presence of sensor noise. A nonlinear Takagi-Sugeno fuzzy model is implemented to create multiple models. While the T-S fuzzy model is used for only the nonlinear distribution matrix of the fault and measurement signals, a larger category of nonlinear systems is considered. Next, a mapping to decou...
متن کاملA Hybrid Approach to Concurrent Error Detection for a Compact ASIC Implementation of the Advanced Encryption Standard
In this paper, we investigate the application of concurrent error detection circuitry to a compact application-specific integrated circuit (ASIC) implementation of the Advanced Encryption Standard (AES). The specific objective of the design is to develop a method suitable for compact ASIC implementations targeted to embedded systems such that the system is resistant to fault attacks. To provide...
متن کامل